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FDS6975 Dual P-Channel, Logic Level, PowerTrenchTM MOSFET
General Description
These P-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance.
These devices are well suited for notebook computer applications: load switching and power management, battery charging circuits, and DC/DC conversion.
Features
• -6 A, -30 V. RDS(ON) = 0.032 W @ VGS = -10 V,
RDS(ON) = 0.045 W @ VGS = -4.5 V.
• Low gate charge (14.5nC typical).
• High performance trench technology for extremely low RDS(ON).
• High power and current handling capability.
Absolute Maximum Ratings TA = 25℃ unless otherwise noted
Symbol | Parameter | Ratings | Units |
---|---|---|---|
VDSS | Drain-Source Voltage | -30 | V |
VGSS | Gate-Source Voltage | ±20 | V |
ID | Drain Current - Continuous (Note 1a) - Pulsed | -6 | A |
-20 | |||
PD | Power Dissipation for Dual Operation | 2 | W |
Power Dissipation for Single Operation (Note 1a) (Note 1b) (Note 1c) | 1.6 | ||
1 | |||
0.9 | |||
TJ ,TSTG | Operating and Storage Temperature Range | -55 to 150 | °C |
THERMAL CHARACTERISTICS
RθJA | Thermal Resistance, Junction-to-Ambient (Note 1a) | 78 | °C/W |
RθJC | Thermal Resistance, Junction-to-Case (Note 1) | 40 | °C/W |
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width ≤ 300µs, Duty Cycle ≤ 2.0%.
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